2T Gain-Cell Memory Buffer- TSMC 40nm

Contributed to the design and verification of readout and peripheral circuitry for an oxide-based 2T gain-cell image-buffer memory in collaboration with an industry partner. Performed transistor-level Spectre simulations to characterize sense-amplifier offset, array leakage, and signal integrity across PVT and Monte Carlo variations. Assisted in automation of pad-ring generation and full-chip integration (200+ I/Os) using mflowgen, incorporating DRC/LVS verification into the design flow.